CoaXPress FPGA IP

Production CoaXPress FPGA IP for camera (device) and frame grabber (host) configurations. CXP-1 through CXP-6 verified; CXP-10/12 on selected architectures. GenICam, multi-lane, multi-stream. Compatible with Intel, AMD, Lattice, and Microchip FPGAs.

CoaXPress FPGA IP block diagram — camera and frame grabber configurations
Category
FPGA IP
Roles
Camera · Frame Grabber
Rates
CXP-1–6 verified · 10/12 capable
Platforms
Intel · AMD · Lattice · Microchip

Camera (device) and frame grabber (host) configurations for integrating CoaXPress into your FPGA design.

CoaXPress Camera (Device) IP

  • CXP-1, 2, 3, 5, 6 already verified
  • CXP-10, 12 capable for some FPGA architectures
  • GenICam command processor with Wishbone interface for integration
  • Integrated GenICam .xml support
  • Capable of any CoaXPress pixel format
  • Pixel FIFO input for integration
  • Single or multi-lane CoaXPress
  • Multi-stream capable
  • Low-speed 8b/10b command protocol implemented in soft logic

CoaXPress Frame Grabber (Host) IP

  • CXP-1, 2, 3, 5, 6 already verified
  • CXP-10, 12 capable for some FPGA architectures
  • GenICam command interface — command FIFO + response FIFO
  • Capable of any CoaXPress pixel format
  • Pixel FIFO output for integration
  • Single- or multi-lane CoaXPress
  • Multi-stream capable
  • Low-speed 8b/10b command protocol implemented in soft logic

Multi-Platform Compatible

  • Intel (Altera)
  • AMD (Xilinx)
  • Lattice
  • Microchip

FPGA Requirements

  • SerDes compatible with CoaXPress 8B/10B data rates

License

  • Standard license is per project with no per-unit fees
  • Pre-compiled modules and source code licenses available
  • Licenses include 8 hours of customization
  • Licenses include one year of support
  • License discounts for multiple licenses

Datasheet

CoaXPress FPGA IP flyer — first page previewDownload CoaXPress IP flyer (PDF)

Gallery

CoaXPress FPGA IP — camera device and frame grabber host block diagrams
Contact us for pricing and availability
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