EEVideo FPGA IP

Tecphos sponsors the open-source Embedded Ethernet Video (EEVideo) protocol and offers FPGA IP that implements it for compact camera and sensor products.

The full protocol specification is published at eevideo.tecphos.com.

A better model for embedded video

For embedded video systems, how you license and tool the stack matters as much as the wire format.

Tecphos pairs:

1. Zero-royalty FPGA IP licensing — license the EEVideo FPGA core per project with no per-unit royalties, so high-volume camera and sensor products are not taxed by protocol IP fees at every device.
2. An open-source protocol specification — design, audit, and interoperate against a public EEVideo spec instead of a closed proprietary stack.
3. Open-source host tooling — discovery, control, scripting, and viewing (goEEVideo, eevid, eevlark, eeview) under permissive licenses for lab, factory, and field use.

That combination is a valuable model for embedded video: predictable device cost, transparent interoperability, and tooling you can modify and ship—without building a one-off Ethernet video stack from scratch or paying vision-suite seat fees for basic bring-up.

Why EEVideo

Embedded systems need a low-complexity, high-capability way to move live video over standard Ethernet—without the heavyweight toolchain of many legacy vision protocols.

EEVideo is built for embedded machine vision: low latency, efficient bandwidth use, flexible formats, and an open specification that teams can adopt without proprietary stack lock-in. The design intentionally keeps device complexity low and puts more capability on the host, which typically has more CPU and software resources.

FPGA IP overview

Tecphos EEVideo FPGA IP implements a soft RISC-V processor to manage the Ethernet IP stack, together with the EEVideo stream and management logic.

A complete FPGA camera path can combine:

• EEVideo IP (including the soft RISC-V stack)
• MIPI receiver
• Key image processing functions

…on FPGAs with fewer than 50k LUTs—suitable for cost-sensitive, high-volume embedded designs.

Low-complexity control plane

EEVideo’s Management Protocol is separate from the stream and is designed for limited-resource devices:

• Host discovery, configuration, and monitoring over Ethernet
• CoAP (IETF Constrained Application Protocol) for compact GET/PUT transactions
• CoRE Link Format for multicast device discovery
• All management interaction as 32-bit register reads and writes in a unified address space
• Feature discovery so a host can learn which optional features exist and where their registers live
• Register 0 carries required device capabilities for quick identification
• Minimal devices can even power up and stream with little or no management interaction on a pre-configured network

Typical host flow: discover → read capabilities → build feature map → configure streams → start stream → monitor/trigger as needed.

Low-complexity UDP stream plane

The Streaming Protocol is optimized for efficiency and latency—not for carrying control:

• Video over standard IP/UDP on ordinary Ethernet hardware
• Lightweight Start-of-Frame / Pixel-Data / End-of-Frame packet structure
• Configurable header sizes (short / medium / long) to balance overhead vs. capability
• Support for flexible pixel formats (bits per pixel, mono / RGB / YUV options)
• Frame and packet IDs for reassembly and diagnostics
• Optional resend / drop flags for robust recovery paths
• Designed for raw or low-latency compressed delivery without mandatory frame buffering on the device

Management uses negligible bandwidth compared with the stream, so the data plane stays simple and fast.

Flexible feature capabilities

EEVideo features are optional and discoverable. Standardized groups cover:

Hosts build a register map from discovery instead of hard-coding every product—useful when you ship many device variants from one software stack.

Open-source libraries and tooling

Cost-effective tooling matters when you deploy thousands of devices. Tecphos supports EEVideo with open-source libraries and tools (MIT-licensed where noted) that run on PCs and on embedded SoCs:

goEEVideo (product page, GitLab) is the Go client library for EEVideo—not a standalone app, but the shared foundation used by eeVid, eevLark, and eeView. It provides UDP CoAP multicast discovery, device YAML generation, high-level register access by name, low-level access by address, field-level writes, and string-register handling. MIT-licensed and installable with go get gitlab.com/eevideo/goeevideo@latest, so you can embed EEVideo control in your own Go applications as well as use the CLI tools.

eeView (product page, GitLab) is an Embedded Ethernet Video stream viewer: it configures a GStreamer pipeline and displays the live stream in a window. Built in Go on goEEVideo under the MIT License, it also supports configuring streaming-related device registers, capturing frames to JPEG, and discovering EEV devices on the network—so bring-up and demos don’t require a proprietary vision suite.

Benefits for product teams:

• Library-first stack — goEEVideo embeds discovery and CoAP register control in custom Go apps; CLIs share the same API
• Discover once, reuse often — discovery builds YAML device maps (capabilities + register names) for reuse
• Same tools from lab to field — CLI binaries and libraries for PC development and embedded SoC deployment
• Register-level access by name, address, or field for bring-up and production test
• Live viewing with GStreamer via eeview, plus stream capture to raw or JPEG
• Scriptable production sequences (init, configure sensor over I2C, start stream, capture) via eevlark
• Permissive MIT licensing so you can modify, rebuild, and ship tooling with your product
• Scale to many devices without per-seat vision-suite licensing for basic control, view, and capture

Highlights

• Zero-royalty FPGA IP licensing (per project, no per-unit fees) plus open spec and open-source tooling
• Open EEVideo protocol sponsored by Tecphos
• FPGA IP with soft RISC-V Ethernet stack management
• Full EEVideo + MIPI + image processing paths under ~50k LUTs
• CoAP / CoRE low-complexity control plane and 32-bit feature registers
• Efficient UDP stream packets (SoF / data / EoF) for low latency
• Discoverable feature set (streams, timing, peripherals, processing, custom)
• Open-source eeVid, eevLark, goEEVideo, and eeView (GStreamer viewer) ecosystem

Demo video

Edge AI and Vision Alliance feature of Tecphos video over Ethernet on a Lattice CrossLink-NX FPGA (uncompressed + on-chip JPEG over one Gigabit Ethernet link, microsecond-class latency):

Related products

• CrossLink-NX Embedded Ethernet Video Dev Board — EEVideo device development hardware
• MIPI FPGA IP — purpose-built MIPI sensor interfaces
• CM3 FPGA Register System IP — Wishbone register fabric used with Tecphos imaging IP
• EEVideo Specification — open protocol documentation

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